1. Field of the Invention
The present invention relates to a clock distribution circuit and a method of forming a clock distribution circuit.
2. Description of the Related Art
Recently, with miniaturization of semiconductor integrated circuits, the problem of manufacturing variations due to new factors, which need not be considered at the design stage in a conventional semiconductor process, has greatly influenced circuit design. In a process in a generation that has not advanced much in terms of miniaturization, statistical distributions of individual differences due to lots, wafers, materials, and the like, have been generally handled as variations.
In a process which has advanced in miniaturization from the 90 nm generation, consideration must be given to a case in which voltage drops and working accuracy influence the electrical characteristics of transistors and wirings in chips, as factors for variations, in addition to the above individual differences at the design stage. That is, since these factors for variations influence the accuracy of timing, it is necessary to impose the design restriction of having to take larger timing margins.
Differences in electrical characteristics, in particular, become a direct factor for deterioration in clock skew, and a timing margin, which is used for a countermeasure against variations provided for a path difference, uses many timings in a cycle span/duration in a place where the path after clock branching is long such as the I/F between blocks.
To cope with such a situation, when designing a synchronous circuit based on clocks, for example, the implementation form disclosed in Japanese Patent Laid-Open No. 2007-336003 is used as a method of regulating the phase of a terminal sequential circuit driven by clocks by using a plurality of phase regulation mechanisms such as PLLs or DLLs in a chip.
In this case, although phase regulation mechanisms such as PLLs or DLLs generally use feedback loop delays, individual designing for the terminal sequential circuits driven by clocks may lead to insufficient phase regulation.
For this reason, the technique disclosed in Japanese Patent Laid-Open No. 2007-336003 uses part of a clock path to a specific sequential circuit as a common path for feedback loop paths.
In addition, there is available an arrangement which compares the phase of a reference clock with the phases of a plurality of feedback paths output from a plurality of clock trees to regulate the delays of the respective clocks (Japanese Patent Laid-Open No. 2008-010607). There is also available an arrangement for regulating the phase control amount of DLL feedback operation using external clocks and an adder (Japanese Patent Laid-Open No. 2000-124795).
With the current tendency toward further miniaturization, however, there is a situation in which consideration must be given to the problem of variations, at the design stage, which occur in manufacturing processes of exposing mask patterns, forming thin films to form elements and wirings, polishing, and the like.
That is, even if a circuit is laid out with elements and wirings having the same structures, it becomes impossible to neglect, at the stage of design, variations, i.e., changes in shape and electrical characteristics, due to layout positions and the influences of neighboring circuits. It is difficult to accurately predict, at the design stage, the influences of variations occurring in these manufacturing processes because the variations are associated with both a systematic factor and a random factor.
According to a conventional method of forming feedback loop paths for phase regulation mechanisms such as PLLs or DLLs, when a single feedback loop path causes a timing problem due to variations in manufacturing processes, since there is no arrangement for phase regulation, faults tend to occur.